University of California, Berkeley
COMPSCI 152 — Computer Architecture and Engineering
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Tool Flow for FPGA CAD
Codes for Error Correction
Processor Design with DSP
Single Cycle Control Design
Multicycle Processor Design
Problem Set for CS 152
Final Class Project
Final Project Report Computer Architecture
FLEET Overview
Superscalars Advanced Out-of-Order
Pin Assignments for Xilinx
Caches and Virtual Memory
ILP, VLIW, and Statically Scheduled Machines
Synchronization and Sequential Consistency
Implementations of Simple Machines
Design Concepts and MIPS ISA Review
Solution to Quiz
Solutions for Quiz 5
Solutions for Quiz 4
Second Pipelining Lecture
Pipelining Part 2
Branch Prediction and Out-of-Order Execution
Multicycle Controller Architecture
Part 2 of Memory Hierarchy