Low Power Processors: Hardware Accelerator Store

Fundamentals of Verilog (Part 1)

Synopsys VCS for Verilog RTL Simulation

Folded and Simple Inelastic Pipelines

SMIPS Core SIMD Extensions

Clock Domains (Multiple)

Processor Simulation and Modeling

Lecture Notes for Complex Digital Systems

Concurrency Issues in IP Lookup

Three-Stage Implementation

Concurrency Issues in Elastic Pipelines

Impact of Design

PowerPC Data Movement Control

Digital Systems of Complexity

Bluespec Combinational Circuits

Simple Synchronous Pipelines and Combinational Circuits

Bluespec-2 Type System

Types in Bluespec-2

Superscalar Timing Model

Basic Verilog 1

Study Notes for Complex Systems

Notes on Digital Systems Study

Guide to Complex Digital Systems

Processor with Runahead