Massachusetts Institute of Technology
6 375 — Complex Digital Systems
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System Modules and Interfaces
Modular Refinement Concepts
Processors and Modeling
Modeling of Digital Processors
Lecture Series Notes
Class Notes: Complex Digital Systems
SMIPSv2 Processor Pipelining: Part 1 (Lab 5)
Design of Encoders
Multi-rule Systems Basics and Elastic Pipelines
Facilitating Rapid SoC Growth through Design
Everything Affected by Design
Pipelines: Asynchronous
Verilog 2 Design Examples
Basic Verilog 1 Concepts
Buffer of Completion
Gates Synthesis from RTL
Processor Modeling
Lookup of IP
Scale-Space Pyramids: Difference of Gaussian
Pipelines: Dead Cycles, Forwarding, and Bubbles
Digital Systems: Complex
Digital Systems Complexity
Bluespec Semantics (Bluespec-7)
Designing Advanced Processors