Hardware Accelerator for Ray Tracing

Specifications of Performance

Bluespec Implementation of Ogg Vorbis

Interfaces and Modules

Placement, Routing, and Logic Synthesis

Notes on Complex Digital Systems

Design Examples in Verilog 2

Methodology for Design: Need for New Approach

Verilog RTL Simulation with Synopsys VCS

Runahead Processing

Spinal Codes in Rateless Wireless Networking

Predictor of Luma

SOPC Builder IP Import

Codesign of Hardware and Software

Methods for Rapid SoC Growth

Issues of Concurrency

Designing Combinational Circuits with Bluespec

Synthesis and Rule Scheduling in Bluespec-4

Fundamentals of Verilog 1

Study Guide: Complex Digital Systems

Specification of SMIPS Processor

Decoder for Rateless Wireless Networking

Flow of Physical Design

Domains of Multiple Clocks