Virtuoso Layout Editing

Editing Layouts in Virtuoso

Lecture 1 Intro

Introduction (Lecture One)

Ratioed Logic and Adders (Lec 14)

Logical Effort CMOS Optimization (Lec 14)

Pass Transistor Logic (Lec 16)

Design Metrics (Lecture 2)

Metrics for Design (Lec 2)

Latches and Flops (Lec 22)

Sequential Circuits (Lec 21)

Sequential Logic Timing (Lecture 23)

Lecture 24 TimingClock Dist.

Timing & Clock Dist. (Lec 24)

IO and Power Distribution (Lec 25)

Adders (Lecture 27)

Lecture 3 CMOS Inverters

DRAM, Flash, & ROM (Lec 29)

Perspectives (Lecture 30)

CMOS SwitchesGates Rules (Lec 4)

Lecture 5 MOS Transistors

Delay and Inverter VTC (Lec 6)

Power Dissipation & Prop Delay (Lec 7)

General Lecture Notes