University of California, Berkeley
ELENG 141 — Introduction to Digital Integrated Circuits
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Sequential Logic (Lecture 22)
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ROM, Adders, & Multipliers (Lec 28)
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Prop Delay & MOS Caps (Lec 6)
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Model of MOS Transistor (Lec 5)
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Lecture Eight Notes
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Course Lecture Notes
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Effort of Logic
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Buffer Sizing and Power
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Energy Analysis (Project 1)
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Tutorial Schematics
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Design of Speed-Area Optimized 8-bit Adder
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Simulation at Switch Level
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Process of CMOS Manufacturing
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Design Measurement Metrics
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MOS Transistor Model and CMOS Inverter Design Rules
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Discussion Session One
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Example 1 Project 2
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Project Phase Two
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First Project
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Project One
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Part 1 FIR Filter Project
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Assignment One
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Weekly Homework
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InputOutput Systems
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