Part 1 High-Level Design

Optimization and High-Level Design II

Finite State Machines Part 2 (Lecture 20)

Lecture 2 Notes CMOS

Introduction to CMOS

Circuit Timing Analysis (Lecture 18)

Lecture 14 Project Outline

Project Description 3

Note 12 Timing

Lecture 11 Description of Project

Lecture 10 on Timing

Combinational Logic Circuits I (Lecture 10)

Intro Lecture 01

Putting It Together (Lecture 19)

Logistics of Lab and FPGA Editor

Finite State Machine on Xilinx (Lab 3)

Lab 2 FSM

Introduction to Xilinx Software (Lab 1)

Introduction to Software for Xilinx Design

CS 150 Assignment

Verilog FSMs and Miscellaneous Topics

LFSRs and Error Correction Codes

Digital TV Encoding Parameters for Studios

Designing Digital Interfaces