CAD Part I Logic Synthesis

Combinational Logic Representations Boolean Algebra I

Lecture 26 ECCs and LFSRs

Arithmetic Blocks Part II and Shifters

CMOS Logic Basics

Power Consumption (Lecture 16)

Dynamic RAM (Lecture 14)

State Elements Sequential Circuits I

Project Description 1

Timing Concepts (Lecture 12)

CPU Microarchitecture (Lecture 10)

Timing Lecture

Eighth Lab Lecture

Test Equipment Lab Lecture

MIDI Interface Lab

FSMs on Xilinx Lab 3

Lab 3 Finite State Machine Implementation

FSM Lab Session 2

Lab 2 Finite State Machines

Designing with Verilog Lab 2

Lab 1 Materials

FPGA Editor Lab

Lab Session 1

Verilog Hardware Description Languages